A liquid crystal display (LCD) is a flat-panel display that has a number of advantageous features including high resolution, drastically reduced thickness and weight, and low power dissipation. The LCD market has been rapidly expanding recently as a result of tremendous improvements in its display performance, significant increases in its productivity, and a noticeable rise in its cost effectiveness over competing technologies.
Among other things, an inplane switching (IPS) mode liquid crystal display device (see Patent Document No. 1) and a multi-domain vertical aligned (MVA) mode liquid crystal display device (see Patent Document No. 2) are often used in liquid crystal TV monitors as a wide viewing angle mode liquid crystal display device that can avoid problems such as a significant decrease in contrast ratio or the inversion of display grayscales, which will happen when the image on the screen is viewed obliquely.
Although the display qualities of LCDs have been further improved nowadays, a viewing angle characteristic problem in a different phase has arisen just recently.
Specifically, the γ characteristic of LCDs would vary with the viewing angle. That is to say, the γ characteristic when an image on the screen is viewed straight is different from the characteristic when it is viewed obliquely. As used herein, the “γ characteristic” refers to the grayscale dependence of display luminance. That is why if the γ characteristic when the image is viewed straight is different from the characteristic when the same image is viewed obliquely, then it means that the grayscale display state changes according to the viewing direction. This is a serious problem particularly when a still picture such as a photo is presented or when a TV program is displayed.
The viewing angle dependence of the γ characteristic is more significant in the MVA mode rather than in the IPS mode. According to the IPS mode, however, it is more difficult to make panels that realize a high contrast ratio when the image on the screen is viewed straight with good productivity rather than in the MVA mode. Taking these circumstances into consideration, it is particularly necessary to reduce the viewing angle dependence of the γ characteristic of MVA mode liquid crystal display devices, among other things.
To overcome such a problem, the applicant of the present application disclosed a liquid crystal display device that can reduce the viewing angle dependence of the γ characteristic (or an excessively high contrast ratio of white portions of an image, among other things) by dividing a single pixel into a number of subpixels, and a method for driving such a device in Patent Document No. 3. Such a display or drive mode will sometimes be referred to herein as “area-grayscale display”, “area-grayscale drive”, “multi-pixel display” or “multi-pixel drive”.
Patent Document No. 3 discloses a liquid crystal display device in which storage capacitors Cs are provided for respective subpixels SP of a single pixel P. In the storage capacitors, the storage capacitor counter electrodes (which are connected to CS bus lines) are electrically independent of each other between the subpixels. And by varying the voltages applied to the storage capacitor counter electrodes (which will be referred to herein as “storage capacitor counter voltages”), mutually different effective voltages can be applied to the respective liquid crystal layers of multiple subpixels by utilizing a capacitance division technique.
Hereinafter, the pixel division structure of the liquid crystal display device 200 disclosed in Patent Document No. 3 will be described with reference to FIG. 18. In this example, the liquid crystal display device is supposed to use a TFT as a switching element.
The pixel 10 is split into a subpixel 10a and another subpixel 10b. To the subpixels 10a and 10b, connected are their associated TFTs 16a and 16b and their associated storage capacitors (CS) 22a and 22b, respectively. The gate electrodes of the TFTs 16a and 16b are both connected to the same scan line 12. And the source electrodes of the TFTs 16a and 16b are connected to the same signal line 14. The storage capacitors 22a and 22b are connected to their associated storage capacitor lines (CS bus lines) 24a and 24b, respectively. The storage capacitor 22a includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18a, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24a, and an insulating layer (not shown) arranged between the electrodes. The storage capacitor 22b includes a storage capacitor electrode that is electrically connected to the subpixel electrode 18b, a storage capacitor counter electrode that is electrically connected to the storage capacitor line 24b, and an insulating layer (not shown) arranged between the electrodes. The respective storage capacitor counter electrodes of the storage capacitors 22a and 22b are independent of each other and have such a structure as receiving mutually different storage capacitor counter voltages from the storage capacitor lines 24a and 24b, respectively.
Hereinafter, it will be described with reference to the accompanying drawings on what principle mutually different effective voltages can be applied to the respective liquid crystal layers of the two subpixels 10a and 10b of the liquid crystal display device 200.
FIG. 19 schematically shows the equivalent circuit of one pixel of the liquid crystal display device 200. In this electrical equivalent circuit, the liquid crystal layers of the subpixels 10a and 10b are identified by the reference numerals 13a and 13b, respectively. A liquid crystal capacitor formed by the subpixel electrode 18a, the liquid crystal layer 13a, and the counter electrode 17 will be identified by Clca. On the other hand, a liquid crystal capacitor formed by the subpixel electrode 18b, the liquid crystal layer 13b, and the counter electrode 17 will be identified by Clcb. The same counter electrode 17 is shared by these two subpixels 10a and 10b. 
The liquid crystal capacitors Clca and Clcb are supposed to have the same electrostatic capacitance CLC (V). The value of CLC (V) depends on the effective voltages (V) applied to the liquid crystal layers of the respective subpixels 10a and 10b. Also, the storage capacitors 22a and 22b that are connected independently of each other to the liquid crystal capacitors of the respective subpixels 10a and 10b will be identified herein by Ccsa and Ccsb, respectively, which are supposed to have the same electrostatic capacitance CCS.
In the subpixel 10a, one electrode of the liquid crystal capacitor Clca and one electrode of the storage capacitor Ccsa are connected to the drain electrode of the TFT 16a, which is provided to drive the subpixel 10a. The other electrode of the liquid crystal capacitor Clca is connected to the counter electrode. And the other electrode of the storage capacitor Ccsa is connected to the storage capacitor line 24a. In the subpixel 10b, one electrode of the liquid crystal capacitor Clcb and one electrode of the storage capacitor Ccsb are connected to the drain electrode of the TFT 16b, which is provided to drive the subpixel 10b. The other electrode of the liquid crystal capacitor Clcb is connected to the counter electrode. And the other electrode of the storage capacitor Ccsb is connected to the storage capacitor line 24b. The gate electrodes of the TFTs 16a and 16b are both connected to the scan line 12 and the source electrodes thereof are both connected to the signal line 14.
Portions (a) through (f) of FIG. 20 schematically show the timings of respective voltages that are applied to drive the liquid crystal display device 200.
Specifically, portion (a) of FIG. 20 shows the voltage waveform Vs of the signal line 14; portion (b) of FIG. 20 shows the voltage waveform Vcsa of the storage capacitor line 24a; portion (c) of FIG. 20 shows the voltage waveform Vcsb of the storage capacitor line 24b; portion (d) of FIG. 20 shows the voltage waveform Vg of the scan line 12; portion (e) of FIG. 20 shows the voltage waveform Vlca of the pixel electrode 18a of the subpixel 10a; and portion (f) of FIG. 20 shows the voltage waveform Vlcb of the pixel electrode 18b of the subpixel 10b. In FIG. 20, the dashed line indicates the voltage waveform COMMON (Vcom) of the counter electrode 17.
Hereinafter, it will be described with reference to portions (a) through (f) of FIG. 20 how the equivalent circuit shown in FIG. 19 operates.
First, at a time T1, the voltage Vg rises from VgL to VgH to turn the TFTs 16a and 16b ON simultaneously. As a result, the voltage Vs on the signal line 14 is transmitted to the subpixel electrodes 18a and 18b of the subpixels 10a and 10b to charge the subpixels 10a and 10b with the voltage Vs. In the same way, the storage capacitors Csa and Csb of the respective subpixels are also charged with the voltage on the signal line.
Next, at a time T2, the voltage Vg on the scan line 12 falls from VgH to VgL to turn the TFTs 16a and 16b OFF simultaneously and electrically isolate the subpixels 10a and 10b and the storage capacitors Csa and Csb from the signal line 14. It should be noted that immediately after that, due to the feedthrough phenomenon caused by a parasitic capacitance of the TFTs 16a and 16b, for example, the voltages Vlca and Vlcb applied to the respective subpixel electrodes decrease by approximately the same voltage Vd to:Vlca=Vs−Vd Vlcb=Vs−Vd respectively. Also, in this case, the voltages Vcsa and Vcsb on the storage capacitor lines are:Vcsa=Vcom−Vad Vcsb=Vcom+Vad respectively.
Next, at a time T3, the voltage Vcsa on the storage capacitor line 24a connected to the storage capacitor Csa rises from Vcom−Vad to Vcom+Vad and the voltage Vcsb on the storage capacitor line 24b connected to the storage capacitor Csb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad. As the voltages on the storage capacitor lines 24a and 24b change in this manner, the voltages Vlca and Vlcb applied to the respective subpixel electrodes change into:Vlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad respectively, where Kc=CCS/(CLC(V)+CCS) and × indicates multiplication.
Next, at a time T4, Vcsa falls from Vcom+Vad to Vcom−Vad and Vcsb rises from Vcom−Vad to Vcom+Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change fromVlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad intoVlca=Vs−Vd Vlcb=Vs−Vd respectively.
Next, at a time T5, Vcsa rises from Vcom−Vad to Vcom+Vad and Vcsb falls from Vcom+Vad to Vcom−Vad. That is to say, these voltages Vcsa and Vcsb both change twice as much as Vad again. In this case, Vlca and Vlcb also change fromVlca=Vs−Vd Vlcb=Vs−Vd intoVlca=Vs−Vd+2×Kc×Vad Vlcb=Vs−Vd−2×Kc×Vad respectively.
After that, every time a period of time that is an integral number of times as long as one horizontal scanning period (or one horizontal write period) 1H has passed, the voltages Vcsa, Vcsb, Vlca and Vlcb alternate their levels at the times T4 and T5. Consequently, the effective values of the voltages Vlca and Vlcb applied to the subpixel electrodes become:Vlca=Vs−Vd+Kc×Vad Vlcb=Vs−Vd−Kc×Vad respectively.
Therefore, the effective voltages V1 and V2 applied to the liquid crystal layers 13a and 13b of the subpixels 10a and 10b become:V1=Vlca−Vcom V2=Vlcb−Vcom That is to say,V1=Vs−Vd+Kc×Vad−Vcom V2=Vs−Vd−Kc×Vad−Vcom respectively.
As a result, the difference  V12 (=V1−V2) between the effective voltages applied to the liquid crystal layers 13a and 13b of the subpixels 10a and 10b becomes V12=2×Kc ×Vad (where Kc=CCS/(CLC(V)+CCS)). Thus, mutually different voltages can be applied to the liquid crystal layers 13a and 13b. 
FIG. 21 schematically shows the relation between V1 and V2. As can be seen from FIG. 21, the smaller the V1 value, the bigger  V12 in the liquid crystal display device 200. Since  V12 increases as the V1 value decreases in this manner, the excessively high contrast ratio can be reduced, among other things.
However, if the multi-pixel structure disclosed in Patent Document No. 3 were applied to either a high-resolution LCD TV monitor or a big LCD TV monitor, the oscillating voltage would have a shorter period of oscillation as the resolution or the size of the display panel increases. Thus, it would be increasingly difficult (and expensive) to make a circuit for generating the oscillating voltage, the power dissipation would increase too much, or the influence of waveform blunting due to the electrical load impedance of the CS bus lines would be more and more significant. However, if a plurality of electrically independent CS trunks are arranged and connected to the multiple CS bus lines as disclosed in Patent Document No. 4, one period of oscillation of the oscillating voltage applied to the storage capacitor counter electrodes by way of the CS bus line can be extended.                Patent Document No. 1: Japanese Patent Gazette for Opposition No. 63-21907        Patent Document No. 2: Japanese Patent Application Laid-Open Publication No. 11-242225        Patent Document No. 3: Japanese Patent Application Laid-Open Publication No. 2004-62146 (corresponding to U.S. Pat. No. 6,958,791)        Patent Document No. 4: WO 2006/070829 A1        